8inch SiC Pwodiksyon klas wafer 4H-N SiC substra

Deskripsyon kout:

8-pous SiC substrats yo te itilize nan gwo pouvwa aparèy elektwonik, tankou pouvwa MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), dyod Schottky ak lòt aparèy semiconductor pouvwa.

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Tablo ki anba la a montre espesifikasyon wafers SiC 8 pous nou yo:

8inch N-tip SiC DSP Espesifikasyon
Nimewo	Atik	Inite	Pwodiksyon	Rechèch	Enbesil
1: paramèt
1.1	politip	--	4H	4H	4H
1.2	oryantasyon sifas yo	°	<11-20>4±0.5	<11-20>4±0.5	<11-20>4±0.5
2: paramèt elektrik
2.1	dopant	--	n-tip Azòt	n-tip Azòt	n-tip Azòt
2.2	rezistivite	ohm ·cm	0.015 ~ 0.025	0.01 ~ 0.03	NA
3: paramèt mekanik
3.1	dyamèt	mm	200±0.2	200±0.2	200±0.2
3.2	epesè	μm	500±25	500±25	500±25
3.3	Oryantasyon Notch	°	[1- 100]±5	[1- 100]±5	[1- 100]±5
3.4	Pwofondè Notch	mm	1 ~ 1.5	1 ~ 1.5	1 ~ 1.5
3.5	LTV	μm	≤5 (10mm * 10mm)	≤5 (10mm * 10mm)	≤10 (10mm * 10mm)
3.6	TTV	μm	≤10	≤10	≤15
3.7	Bow	μm	-25 ~ 25	-45 ~ 45	-65 ~ 65
3.8	Defòme	μm	≤30	≤50	≤70
3.9	AFM	nm	Ra≤0.2	Ra≤0.2	Ra≤0.2
4: Estrikti
4.1	dansite micropipe	ea/cm2	≤2	≤10	≤50
4.2	kontni metal	atòm/cm2	≤1E11	≤1E11	NA
4.3	TSD	ea/cm2	≤500	≤1000	NA
4.4	BPD	ea/cm2	≤2000	≤5000	NA
4.5	TED	ea/cm2	≤7000	≤10000	NA
5.Front bon jan kalite
5.1	devan	--	Si	Si	Si
5.2	fini sifas	--	Si-fas CMP	Si-fas CMP	Si-fas CMP
5.3	patikil	ea/wafer	≤100 (gwosè ≥0.3μm)	NA	NA
5.4	grate	ea/wafer	≤5, Total Length≤200mm	NA	NA
5.5	Edge chips / endentasyon / fant / tach / kontaminasyon	--	Okenn	Okenn	NA
5.6	Zòn politip yo	--	Okenn	Zòn ≤10%	Zòn ≤30%
5.7	make devan	--	Okenn	Okenn	Okenn
6: bon jan kalite tounen
6.1	tounen fini	--	C-fas MP	C-fas MP	C-fas MP
6.2	grate	mm	NA	NA	NA
6.3	Retounen domaj kwen chips/tint	--	Okenn	Okenn	NA
6.4	Retounen brutality	nm	Ra≤5	Ra≤5	Ra≤5
6.5	Retounen make	--	Notch	Notch	Notch
7:kwen
7.1	kwen	--	Chanfrein	Chanfrein	Chanfrein
8: pake
8.1	anbalaj	--	Epi-pare ak vakyòm anbalaj	Epi-pare ak vakyòm anbalaj	Epi-pare ak vakyòm anbalaj
8.2	anbalaj	--	Multi-wafer anbalaj kasèt	Multi-wafer anbalaj kasèt	Multi-wafer anbalaj kasèt